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| Features * Supply Voltage 5V * Very Low Power Consumption 125 mW * Very Good Image Rejection By Means of Phase Control Loop for Precise 90 Phase * * * * * * Shifting Duty-cycle Regeneration for Single-ended LO Input Signal Low LO Input Level -10 dBm LO Frequency from 70 MHz to 1 GHz Power-down Mode 25 dB Gain Control Very Low I/Q Output DC Offset Voltage Typically < 5 mV Benefits * Low Current Consumption * Easy to Implement * Perfect Performance for Large Variety of Wireless Applications 1000-MHz Quadrature Demodulator U2794B 1. Description The silicon monolithic integrated circuit U2794B is a quadrature demodulator manufactured using Atmel (R)'s advanced UHF technology. This demodulator features a frequency range from 70 MHz to 1000 MHz, low current consumption, selectable gain, power-down mode, and adjustment-free handling. The IC is suitable for direct conversion and image rejection applications in digital radio systems up to 1 GHz such as cellular radios, cordless telephones, cable TV, and satellite TV systems. Figure 1-1. VS 5,6 Block Diagram PU 14 IIX 4 II 3 1 2 IX OUTPUT I Power down RFin 7 8 90Control loop 0 90 Frequency doubler Duty cycle 15 LO regenerator 17 13 PC 12 19 20 PCX Q OUTPUT QX 11 16,18 10 9 GC GND QQX 4653F-CELL-11/08 2. Pin Configuration Figure 2-1. Pinning SSO20 IX I II IIX V S VS RFin RFXin QQ QQX 1 2 3 4 5 6 7 8 9 10 20 QX 19 18 17 16 15 Q GND LOin GND LOXin 14 PU 13 PC 12 PCX 11 GC Table 2-1. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Description Symbol IX I II IIX VS VS RFin RFXin QQ QQX GC PCX PC PU LOXin GND LOin GND Q QX Function IX output I output II lowpass filter I IIX lowpass filter I Supply voltage Supply voltage RF input RFX input QQ lowpass filter Q QQX lowpass filter Q GC gain control PCX phase control PC phase control PU power up LOX input Ground LO input Ground Q output QX output 2 U2794B 4653F-CELL-11/08 U2794B 3. Absolute Maximum Ratings Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Supply voltage Input voltage Junction temperature Storage-temperature range Symbol VS Vi Tj Tstg Value 6 0 to VS +125 -55 to +125 Unit V V C C 4. Thermal Resistance Parameters Junction ambient SSO20 Symbol RthJA Value 140 Unit K/W 5. Operating Range Parameters Supply-voltage range Ambient-temperature range Symbol VS Tamb Value 4.75 to 5.25 -40 to +85 Unit V C 3 4653F-CELL-11/08 6. Electrical Characteristics Test conditions (unless otherwise specified); VS = 5V, Tamb = 25C, referred to test circuit System impedance ZO = 50, fiLO = 950 MHz, PiLO = -10 dBm No. 1.1 1.2 2 2.1 3 3.1 3.2 4 4.1 4.2 4.3 4.4 4.5 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 Notes: Parameters Supply-voltage range Supply current Power-down Mode "OFF" mode supply current Switch Voltage "Power ON" "Power DOWN" LO Input, LOin Frequency range Input level Input impedance Voltage standing wave ratio Duty-cycle range RF Input, RFin Noise figure (DSB) symmetrical output Frequency range -1 dB input compression point Second order IIP Third order IIP LO leakage Input impedance at 950 MHz(3) at 100 MHz fiRF = fiLO BWYQ High gain Low gain (4) (2) Test Conditions Pin 5, 6 5, 6 Symbol VS IS Min. 4.75 22 Typ. 30 1 20 Max. 5.25 35 Unit V mA A A V Type* A A B D D D D D D D D VPU 0.5V VPU = 1.0 V(1) 14, 5 6 14 14 17 17 17 17 17 ISPU VPON VPOFF fiLO PiLO ZiLO VSWRLO DCRLO 4 1 70 -12 -10 50 1.2 0.4 12 10 40 -8 +3.5 35 +3 +13 -60 -55 500II0.8 1030 2 0.6 1000 -5 V MHz dBm See Figure 6-10 See Figure 6-3 7, 8 7, 8 7, 8 7, 8 7, 8 7, 8 7, 8 NF fiRF P1dBHG P1dBLG IIP2HG IIP3HG IIP3LG LOL ZiRF dB MHz dBm dBm dBm dBm IIpF D D D D D D D High gain Low gain Symmetric input Asymmetric input see Figure 6-10 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 1. During power-down status a load circuitry with DC-isolation to GND is assumed, otherwise a current of I (VS -0.8V)/RI has to be added to the above power-down current for each output I, IX, Q, QX. 2. The required LO-Level is a function of the LO frequency (see Figure 6-6). 3. Measured with input matching. For 950 MHz, the optional transmission line T3 at the RF input may be used for this purpose. Noise figure measurements without using the differential output signal result in a worse noise figure. 4. Using pins 7 and 8 as a symmetric RF input, the second-order IIP can be improved. 5. Due to test board parasitics, this bandwidth may be reduced and not be equal for I, IX, Q, QX. If symmetry and full bandwidth is required, the lowpass pins 3, 4 and 9, 10 should be isolated from the board. the bandwidth of the I/Q outputs can be increased further by using a resistor between pins 3, 4, 9 and 10. These resistors shunt the internal loads of RI ~ 5.4 k. The decrease in gain here has to be considered. 6. The internal current of the output emitter followers is 0.6 mA. This reduces the undistorted output voltage swing at a 50 load to approximately 30 mV. For low signal distortion the load impedance should be RI 5 k. 7. Referred to the level of the output vector I +Q 2 2 8. The low-gain status is achieved with an open or high-ohmic pin 11. A recommended application circuit for switching between high and low gain status is shown in Figure 6-1. 4 U2794B 4653F-CELL-11/08 U2794B 6. Electrical Characteristics (Continued) Test conditions (unless otherwise specified); VS = 5V, Tamb = 25C, referred to test circuit System impedance ZO = 50, fiLO = 950 MHz, PiLO = -10 dBm No. 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 Notes: Parameters 3-dB bandwidth w/o external C I/Q amplitude error I/Q phase error I/Q maximum output swing DC output voltage DC output offset voltage Output impedance Gain Control, GC Control range power Gain high Gain low Switch Voltage "Gain high" "Gain low" Settling Time, ST Power "OFF" - "ON" Power "ON" - "OFF" TSON TSOFF <4 <4 s s D D (8) (7) (6) Test Conditions Pin 1, 2, 19, 20 1, 2, 19, 20 1, 2, 19, 20 Symbol Min. Typ. Max. Unit Type* I/Q Outputs (I, IX, Q, QX) Emitter Follower I = 0.6 mA BWI/Q Ae Pe VPP VOUT Voffset Zout 2.5 2.8 <5 50 30 -0.5 -3 0.2 1.5 +0.5 +3 2 3.1 V mV MHz dB Deg D B B D A Test spec. D Symm. output RL > 5 k 1, 2, 19, 20 1, 2, 19, 20 1, 2, 19, 20 1, 2, 19, 20 see Figure 6-10 11 GCR GH GL 25 23 -2 1 dB dB dB V D B D 11 11 < open *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 1. During power-down status a load circuitry with DC-isolation to GND is assumed, otherwise a current of I (VS -0.8V)/RI has to be added to the above power-down current for each output I, IX, Q, QX. 2. The required LO-Level is a function of the LO frequency (see Figure 6-6). 3. Measured with input matching. For 950 MHz, the optional transmission line T3 at the RF input may be used for this purpose. Noise figure measurements without using the differential output signal result in a worse noise figure. 4. Using pins 7 and 8 as a symmetric RF input, the second-order IIP can be improved. 5. Due to test board parasitics, this bandwidth may be reduced and not be equal for I, IX, Q, QX. If symmetry and full bandwidth is required, the lowpass pins 3, 4 and 9, 10 should be isolated from the board. the bandwidth of the I/Q outputs can be increased further by using a resistor between pins 3, 4, 9 and 10. These resistors shunt the internal loads of RI ~ 5.4 k. The decrease in gain here has to be considered. 6. The internal current of the output emitter followers is 0.6 mA. This reduces the undistorted output voltage swing at a 50 load to approximately 30 mV. For low signal distortion the load impedance should be RI 5 k. 7. Referred to the level of the output vector I +Q 2 2 8. The low-gain status is achieved with an open or high-ohmic pin 11. A recommended application circuit for switching between high and low gain status is shown in Figure 6-1. 5 4653F-CELL-11/08 Figure 6-1. Test Circuit * optional for single-ended tests (notice 3 dB bandwidth of AD620) T1, T2 = transmission line ZO = 50. If no GC function is required, connect Pin 11 to GND. For high and low gain status GC is to be switched to GND respectively to VS. Figure 6-2. I and Q phase for fRF > fLO. For fRF < fLO the phase is inverted. 1.5 I/Q Output Normalized 1.0 Q 0.5 I 0.0 0 -0.5 5 10 15 20 25 30 -1.0 -1.5 Time (Arbitrary Units) 6 U2794B 4653F-CELL-11/08 U2794B Figure 6-3. Typical VSWR Frequency Response of the LO Input 6 5 VSWR 4 3 2 1 50 250 450 650 850 1050 LO Frequency ( MHz ) Figure 6-4. Noise Figure versus LO Frequency; o: Value at 950 MHz with RF Input Matching with T3 18 16 14 NF (dB) 12 10 8 0 200 400 600 800 1000 LO Frequency (MHz) Figure 6-5. Typical Suitable LO Power Range versus Frequency 0 PLOmax -10 PLO (dBm) -20 -30 PLOmin -40 -50 30 40 50 60 70 80 90 LO Frequency (MHz) 7 4653F-CELL-11/08 Figure 6-6. Gain versus LO Frequency; x: Value at 950 MHz with RF Input Matching with T3 30 26 Gain (dB) 22 18 14 10 0 200 400 600 800 1000 LO Frequency (MHz) Figure 6-7. Typical Output Signal versus LO Frequency for PRF = -15 dBm and PLO = -15 dBm 1600 1500 1400 VI/Qout (mVpp) 1300 1200 1100 1000 900 800 0 200 400 600 800 1000 LO Frequency (MHz) Figure 6-8. Typical Suitable LO Power Range versus Frequency 10 0 -10 PLO (dBm) -20 -30 -40 -50 0 200 400 600 800 1000 LO Frequency (MHz) 8 U2794B 4653F-CELL-11/08 U2794B Figure 6-9. Typical Output Voltage (Single Ended) versus PRF at Tamb = 25C and PLO = -15 dBm 1800 1600 1400 VI/Qout (mVpp) 1200 1000 800 600 400 200 0 -40 -35 -30 -25 -20 -15 -10 PRF (dBm) Figure 6-10. Typical S11 Frequency Response j 0.5j 2j 0.2j 5j 0 0.2 0.5 a a 1 c c 2 5 1 bb -0.2j -5j -0.5j -j -2j a: LO input, LO frequency from 100 MHz to 1100 MHz, marker: 950 MHz b: RF input, RF frequency from 100 MHz to 1100 MHz, marker: 950 MHz c: I/Q Outputs, Baseband Frequency from 5 MHz to 55 MHz, marker: 25 MHz 9 4653F-CELL-11/08 Figure 6-11. Evaluation Board Layout Figure 6-12. Evaluation Board 10 U2794B 4653F-CELL-11/08 U2794B 6.1 External Components CUCC CRFX CLO CNLO CRF CII, CQQ T3 CI, CIX CQ, CQX CPDN CGC CPC CNPC GSW 100 nF 1 nF 100 pF 1 nF 100 pF optional external lowpass filters transmission line for RF-input matching, to connect optionally optional for AC-coupling at baseband outputs not connected not connected not connected gain switch 100 pF 100 pF 100 pF 100 pF 6.2 Calibration Part CO, CS, CL RL 100 pF 50 6.3 Conversion to Single Ended Output (see datasheet of AD620) OP1, OP2 RG1, RG2 RD1, RD2 CS1, CS2 CS3, CS4 450 100 nF 100 nF AD620 prog. gain, see datasheet, for 5.6 k a gain of 1 at 50 is achieved together with RD1 and RD2. 11 4653F-CELL-11/08 7. Description of the Evaluation Board Board material: epoxy; r = 4.8, thickness = 0.5 mm, transmission lines: ZO = 50 The board offers the following functions: * Test circuit for the U2794B: - The supply voltage and the control inputs GC, PC, and PU are connected via a plug strip. The control input voltages can be generated via external potentiometers; then the inputs should be AC-grounded (time requirements in burst mode for power up have to be considered). - The outputs I, IX, Q, QX are DC coupled via an plug strip or can be AC-connected via SMB plugs for high frequency tests e.g. noise figure or s-parameter measurement. The Pins II, IIX, QQ, QQX allow user-definable filtering with 2 external capacitors CII, CQQ. - The offsets of both channels can be adjusted with two potentiometers or resistors. - The LO and the RF-inputs are AC-coupled and connected via SMB plugs. If transmission line T3 is connected to the RF-input and AC-grounded at the other end, gain and noise performance can be improved (input matching to 50). - The complementary RF-input is AC-coupled to GND (CRFX = 1 nF), the same appears to the complementary LO input (CNLO = 1 nF). * A calibration part which allows to calibrate an s-parameter analyzer directly to the in- and output- signal ports of the U2794B. * For single-ended measurements at the demodulator outputs, two OPs (e.g., AD620 or other) can be configured with programmable gain; together with an output-divider network RD = 450 to RL = 50, direct measurements with 50 load impedances are possible at frequencies t < 100 kHz. 12 U2794B 4653F-CELL-11/08 U2794B 8. Ordering Information Extended Type Number U2794B-NFSH U2794B-NFSG3H Package SSO20 SSO20 Remarks Tube, MOQ 830 pcs, Pb-free Taped and reeled, MOQ 4000 pcs, Pb-free 9. Package Information 5.40.2 6.75-0.25 4.40.1 0.05+0.1 1.30.05 0.250.05 0.650.05 5.850.05 6.450.15 20 11 Package: SSO20 Dimensions in mm technical drawings according to DIN specifications 1 10 Drawing-No.: 6.543-5056.01-4 Issue: 1; 10.03.04 0.150.05 13 4653F-CELL-11/08 10. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4653F-CELL-11/08 History * Put datasheet in the newest template * ESD logo on page 1 deleted * Section 6 "Electrical Characteristics" number 7.1 on page 6 changed * Put datasheet in the newest template * Section 3 "Absolute Maximum Ratings": Storage temperature values on page 4 changed. 4653E-CELL-07/06 14 U2794B 4653F-CELL-11/08 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-en-Yvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support cell_phone@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. (c) 2008 Atmel Corporation. All rights reserved. Atmel (R), Atmel logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 4653F-CELL-11/08 |
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